PCB - Ram connectors problem
Currently following an schematic for NanoPI NEO4 to make my own RK3399 board.
On their schematic for the K4B4G1646D-BCK0,I noticed for pins DQ1-DQ15 on both chips connect to a randomised list of connectors from DDR0_D1 to DDR0_D31 and I was wondering why is that?
And also why are the numbers on the connectors different to the lines that they're connecting to, for example DQ7 I would expect it to connect to DDR0_D7 but instead it connects to DDR0_D3.
Second question in relation to the LDQS(F3)/LDQSN(G3) & UDQS(C7)/UDQSN(B7) connectors I plan to change out the ram chips for a different chip which is more widely available to purchase (AS24C256M16D3LB-BIN); however I've noticed that the LDQS/LDQSN & UDQS/UDQSN pins are completely missing from the datasheet and instead have been replaced with DQSL (F3/G3) & DQSU (C7/B7). So I was wondering how do I exactly go about connecting these up to the previously available connectors on the RK3399?
Finally I noticed on the manifesto for the Nanopi Neo4 that its meant to use 1GB of DDR3 Ram but in the schematic these K4B4G1646D-BCK0 are actually 4GB each so I was curious as to whether the wiring they have in their schematic for the DDR Controller on the RK3399 & DDR3 schematic properly utilises the 2 4GB DDR3 ram and allows the RK3399 to have the 8GB DDR3 ram readily available?
If anyone able to help answer and/or point in the direction of an answer, would be greatly appreciated.
DDR3 RAM Schematic
DDR Controller
AS24C256M16D3LB-BIN
pcb-assembly ram ddr3
asked 4 hours ago
Dragonfly3rDragonfly3r
354
add a comment |
Currently following an schematic for NanoPI NEO4 to make my own RK3399 board.
On their schematic for the K4B4G1646D-BCK0,I noticed for pins DQ1-DQ15 on both chips connect to a randomised list of connectors from DDR0_D1 to DDR0_D31 and I was wondering why is that?
And also why are the numbers on the connectors different to the lines that they're connecting to, for example DQ7 I would expect it to connect to DDR0_D7 but instead it connects to DDR0_D3.
Second question in relation to the LDQS(F3)/LDQSN(G3) & UDQS(C7)/UDQSN(B7) connectors I plan to change out the ram chips for a different chip which is more widely available to purchase (AS24C256M16D3LB-BIN); however I've noticed that the LDQS/LDQSN & UDQS/UDQSN pins are completely missing from the datasheet and instead have been replaced with DQSL (F3/G3) & DQSU (C7/B7). So I was wondering how do I exactly go about connecting these up to the previously available connectors on the RK3399?
Finally I noticed on the manifesto for the Nanopi Neo4 that its meant to use 1GB of DDR3 Ram but in the schematic these K4B4G1646D-BCK0 are actually 4GB each so I was curious as to whether the wiring they have in their schematic for the DDR Controller on the RK3399 & DDR3 schematic properly utilises the 2 4GB DDR3 ram and allows the RK3399 to have the 8GB DDR3 ram readily available?
If anyone able to help answer and/or point in the direction of an answer, would be greatly appreciated.
DDR3 RAM Schematic
DDR Controller
AS24C256M16D3LB-BIN
pcb-assembly ram ddr3
asked 4 hours ago
Dragonfly3rDragonfly3r
354
"... its meant to use 1GB of DDR3 Ram but in the schematic these K4B4G1646D-BCK0 are actually 4GB ..." - Gigabytes, or gigabits? Check carefully ;)
– marcelm
2 hours ago
add a comment |
Currently following an schematic for NanoPI NEO4 to make my own RK3399 board.
On their schematic for the K4B4G1646D-BCK0,I noticed for pins DQ1-DQ15 on both chips connect to a randomised list of connectors from DDR0_D1 to DDR0_D31 and I was wondering why is that?
And also why are the numbers on the connectors different to the lines that they're connecting to, for example DQ7 I would expect it to connect to DDR0_D7 but instead it connects to DDR0_D3.
Second question in relation to the LDQS(F3)/LDQSN(G3) & UDQS(C7)/UDQSN(B7) connectors I plan to change out the ram chips for a different chip which is more widely available to purchase (AS24C256M16D3LB-BIN); however I've noticed that the LDQS/LDQSN & UDQS/UDQSN pins are completely missing from the datasheet and instead have been replaced with DQSL (F3/G3) & DQSU (C7/B7). So I was wondering how do I exactly go about connecting these up to the previously available connectors on the RK3399?
Finally I noticed on the manifesto for the Nanopi Neo4 that its meant to use 1GB of DDR3 Ram but in the schematic these K4B4G1646D-BCK0 are actually 4GB each so I was curious as to whether the wiring they have in their schematic for the DDR Controller on the RK3399 & DDR3 schematic properly utilises the 2 4GB DDR3 ram and allows the RK3399 to have the 8GB DDR3 ram readily available?
If anyone able to help answer and/or point in the direction of an answer, would be greatly appreciated.
DDR3 RAM Schematic
DDR Controller
AS24C256M16D3LB-BIN
pcb-assembly ram ddr3
asked 4 hours ago
Dragonfly3rDragonfly3r
354
Currently following an schematic for NanoPI NEO4 to make my own RK3399 board.
On their schematic for the K4B4G1646D-BCK0,I noticed for pins DQ1-DQ15 on both chips connect to a randomised list of connectors from DDR0_D1 to DDR0_D31 and I was wondering why is that?
And also why are the numbers on the connectors different to the lines that they're connecting to, for example DQ7 I would expect it to connect to DDR0_D7 but instead it connects to DDR0_D3.
Second question in relation to the LDQS(F3)/LDQSN(G3) & UDQS(C7)/UDQSN(B7) connectors I plan to change out the ram chips for a different chip which is more widely available to purchase (AS24C256M16D3LB-BIN); however I've noticed that the LDQS/LDQSN & UDQS/UDQSN pins are completely missing from the datasheet and instead have been replaced with DQSL (F3/G3) & DQSU (C7/B7). So I was wondering how do I exactly go about connecting these up to the previously available connectors on the RK3399?
Finally I noticed on the manifesto for the Nanopi Neo4 that its meant to use 1GB of DDR3 Ram but in the schematic these K4B4G1646D-BCK0 are actually 4GB each so I was curious as to whether the wiring they have in their schematic for the DDR Controller on the RK3399 & DDR3 schematic properly utilises the 2 4GB DDR3 ram and allows the RK3399 to have the 8GB DDR3 ram readily available?
If anyone able to help answer and/or point in the direction of an answer, would be greatly appreciated.
DDR3 RAM Schematic
DDR Controller
AS24C256M16D3LB-BIN
pcb-assembly ram ddr3
pcb-assembly ram ddr3
asked 4 hours ago
Dragonfly3rDragonfly3r
354
asked 4 hours ago
Dragonfly3rDragonfly3r
354
asked 4 hours ago
Dragonfly3rDragonfly3r
354
asked 4 hours ago
Dragonfly3rDragonfly3r
354
asked 4 hours ago
Dragonfly3rDragonfly3r
354
354
"... its meant to use 1GB of DDR3 Ram but in the schematic these K4B4G1646D-BCK0 are actually 4GB ..." - Gigabytes, or gigabits? Check carefully ;)
– marcelm
2 hours ago
add a comment |
"... its meant to use 1GB of DDR3 Ram but in the schematic these K4B4G1646D-BCK0 are actually 4GB ..." - Gigabytes, or gigabits? Check carefully ;)
– marcelm
2 hours ago
"... its meant to use 1GB of DDR3 Ram but in the schematic these K4B4G1646D-BCK0 are actually 4GB ..." - Gigabytes, or gigabits? Check carefully ;)
– marcelm
2 hours ago
"... its meant to use 1GB of DDR3 Ram but in the schematic these K4B4G1646D-BCK0 are actually 4GB ..." - Gigabytes, or gigabits? Check carefully ;)
– marcelm
2 hours ago
add a comment |
1 Answer
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The order of the data bits going to a memory doesn't really matter, as long as you read back the same bits you've written. The memory chips themselves don't care which bit is which. (You can't say the same thing for the address bus, however.)
The designer probably picked the "random" order in order to improve the PCB layout. Doing so may have solved both physical routing issues as well as timing issues.
answered 3 hours ago
Dave Tweed♦Dave Tweed
118k9145256
add a comment |
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1 Answer
1
active
oldest
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oldest
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oldest
votes
The order of the data bits going to a memory doesn't really matter, as long as you read back the same bits you've written. The memory chips themselves don't care which bit is which. (You can't say the same thing for the address bus, however.)
The designer probably picked the "random" order in order to improve the PCB layout. Doing so may have solved both physical routing issues as well as timing issues.
answered 3 hours ago
Dave Tweed♦Dave Tweed
118k9145256
add a comment |
The order of the data bits going to a memory doesn't really matter, as long as you read back the same bits you've written. The memory chips themselves don't care which bit is which. (You can't say the same thing for the address bus, however.)
The designer probably picked the "random" order in order to improve the PCB layout. Doing so may have solved both physical routing issues as well as timing issues.
answered 3 hours ago
Dave Tweed♦Dave Tweed
118k9145256
add a comment |
The order of the data bits going to a memory doesn't really matter, as long as you read back the same bits you've written. The memory chips themselves don't care which bit is which. (You can't say the same thing for the address bus, however.)
The designer probably picked the "random" order in order to improve the PCB layout. Doing so may have solved both physical routing issues as well as timing issues.
answered 3 hours ago
Dave Tweed♦Dave Tweed
118k9145256
The order of the data bits going to a memory doesn't really matter, as long as you read back the same bits you've written. The memory chips themselves don't care which bit is which. (You can't say the same thing for the address bus, however.)
The designer probably picked the "random" order in order to improve the PCB layout. Doing so may have solved both physical routing issues as well as timing issues.
answered 3 hours ago
Dave Tweed♦Dave Tweed
118k9145256
answered 3 hours ago
Dave Tweed♦Dave Tweed
118k9145256
answered 3 hours ago
Dave Tweed♦Dave Tweed
118k9145256
answered 3 hours ago
Dave Tweed♦Dave Tweed
118k9145256
118k9145256
add a comment |
add a comment |
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"... its meant to use 1GB of DDR3 Ram but in the schematic these K4B4G1646D-BCK0 are actually 4GB ..." - Gigabytes, or gigabits? Check carefully ;)
– marcelm
2 hours ago